Device Package with Reduced Thickness and Method for Forming Same

ABSTRACT

A device package includes a die and a molding compound around the die. The molding compound has a non-planar surface recessed from a top surface of the die. The device package also includes an interconnect structure over the die. The interconnect structure includes a redistribution layer extending onto the molding compound and conformal to the non-planar surface of the molding compound. The device package further includes a first connector disposed over the die and bonded to the interconnect structure.

RELATED CASE

This application is related to commonly assigned and co-pending U.S. patent application Ser. No. 14/464,487, filed on Aug. 20, 2014, and entitled, “Interconnect Structures for Wafer Level Package and Methods of Forming Same,” which application is incorporated herein by reference.

BACKGROUND

In an aspect of conventional packaging technologies, such as wafer level packaging (WLP), an interconnect structure, including redistribution layers (RDLs), may be formed over a die and electrically connected to active devices in a die. An advantageous feature of this packaging technology is the possibility of forming a fan-out interconnect structure. For example, I/O pads on a die can be redistributed to a greater area than the die, and hence the number of I/O pads packed on the surfaces of the dies can be increased.

In such packaging technologies, a molding compound may be formed around the die to provide extra surface area for supporting the fan-out interconnect structure. RDLs of the interconnect structure electrically connect I/O pads on the die to the external I/O pads on the fan-out interconnect structure. The external I/O pads may be disposed over both the die and the molding compound.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 illustrates a cross-sectional view of a device package in accordance with some embodiments.

FIGS. 2 through 9 illustrate cross-sectional views of intermediary steps of manufacturing a device package in accordance with some embodiments.

FIGS. 10 through 15 illustrate cross-sectional views of device packages in accordance with some other embodiments.

FIG. 16 illustrates a method for forming a device package in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Described below is a method for forming a device package and corresponding structure. In some embodiments, a molding compound is formed around a die using a transfer molding process. After the molding compound is formed, a top surface of the die may remain exposed. The formed molding compound may include a non-planar top surface. Afterwards, a fan-out interconnect structure is formed directly over the die and the molding compound. The fan-out interconnect structure extends beyond a boundary of the die to provide an extra area for retribution. A planarization layer for planarizing the molding compound is not needed. Overall thickness and manufacturing cost of the device package may be reduced.

FIG. 1 illustrates a cross-sectional view of a device package 100 in accordance with some embodiments. Device package 100 includes a die 102 and a molding compound 104 disposed around die 102. A fan-out interconnect structure 116 is formed over die 102 and extends onto molding compound 104. Die 102 may be a semiconductor die and could be any type of integrated circuit, such as a processor, logic circuitry, memory, analog circuit, digital circuit, mixed signal, and the like. In some embodiments, die 102 includes a substrate, active devices, and an interconnect structure (not individually illustrated). The substrate may include bulk silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. Generally, an SOI substrate includes a layer of a semiconductor material, such as silicon, formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer or a silicon oxide layer. The insulator layer is provided on a substrate, such as a silicon or glass substrate. Alternatively, the substrate may include another elementary semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used.

Active devices such as transistors, capacitors, resistors, diodes, photo-diodes, fuses, and the like may be formed at the top surface of the substrate. An interconnect structure may be formed over the active devices and the substrate. The interconnect structure may include inter-layer dielectric (ILD) and/or inter-metal dielectric (IMD) layers containing conductive features (e.g., conductive lines and vias comprising copper, aluminum, tungsten, combinations thereof, and the like) formed using any suitable method. The ILD and IMDs may include low-k dielectric materials having k values, for example, lower than about 4.0 or even 2.0 disposed between such conductive features. In some embodiments, the ILD and IMDs may be made of, for example, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), SiO_(x)C_(y), Spin-On-Glass, Spin-On-Polymers, silicon carbon material, compounds thereof, composites thereof, combinations thereof, or the like, formed by any suitable method, such as spinning, chemical vapor deposition (CVD) and plasma-enhanced CVD (PECVD). The interconnect structure electrically connects various active devices to form functional circuits within die 102. The functions provided by such circuits may include memory structures, processing structures, sensors, amplifiers, power distribution, input/output circuitry, or the like. One of ordinary skill in the art will appreciate that the above examples are provided for illustrative purposes only to further explain applications of the present disclosure and are not meant to limit the present disclosure in any manner. Other circuitry may be used as appropriate for a given application.

Die 102 may further include input/output (I/O) and passivation features formed over the interconnect structure. For example, pads 110 may be formed at the top surface of die 102. Pads 110 are electrically connected to the active devices through the various conductive features in the interconnect structure. Pads 110 include a conductive material such as aluminum, copper, and the like. Pads 110 may be surrounded by a passivation layer 112. In some embodiments, passivation layer 112 covers edge portions of pads 110. Passivation layer 112 includes silicon oxide, un-doped silicate glass, silicon oxynitride, polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB) although other suitable passivation materials may also be used. In some embodiments, passivation layer 112 has a thickness ranging from about 1 μm to about 100 μm.

Molding compound 104 is disposed around die 102. For example, in a top down view of molding compound 104/die 102 (not illustrated), molding compound 104 may encircle die 102. As will be described in greater detail in subsequent paragraphs, molding compound 104 may be formed using a transfer molding process, which does not cover a top surface of die 102. In addition, molding compound 104 includes a non-planar top surface recessed from the top surface of die 102, in some embodiments. Top surface 104A of molding compound 104 may be a non-planar portion (e.g., curved or linear inclined portion) recessed from top surface 112A of passivation layer 112, for example. In some embodiments, top surface 104A further includes a substantially flat portion on a side of the non-planar portion of molding compound 104 away from die 102. Non-planar top surface 104A of molding compound 104 may have a total thickness variation T (e.g., distance between a highest point and a lowest point of the top surface) of about 1 μm to about 10 μm, for example. In some embodiments, there is no abrupt slope change on top surfaces 112A and 104A of passivation layer 112 and molding compound 104 and the interface therebetween. Molding compound 104 may include epoxy, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO) or a combination thereof, with or without filler embedded therein. The filler may include carbon filler or glass filler.

An interconnect structure 116 is disposed over die 102. For example, the interconnect structure 116 may include a redistribution layer 116R disposed over pads 110 and passivation layer 112. Redistribution layer 116R may extend outside a boundary of die 102 and onto molding compound 104. Thus, interconnect structure 116 enables a fan-out function for die 102 and is thereby sometimes called as a fan-out interconnect structure 116. Redistribution layer 116R includes contact pads 116B₁ over the die 102 (i.e., inside the boundary of die 102), contact pads 116B₂ over molding compound 104 (i.e., outside the boundary of die 102) and redistribution lines 116C electrically connecting contact pads 116B₁ and 116B₂ to pads 110. In some embodiments, redistribution layer 116R is directly formed on die 102 and molding compound 104A with no planarization layer interposed therebetween. Redistribution lines 116R and contact pads 116B₂ may be in direct contact with and conformal to non-planar top surface 104A of molding compound 104. In some embodiments, contact pads 116B₁ and 116B₂ and redistribution lines 116R is formed copper or copper alloy. Alternatively, contact pads 116B₁ and 116B₂ and redistribution lines 116R include aluminum, titanium, titanium nitride or other suitable conductive materials.

Additional package features, such as connectors 120, are mounted to contact pads 16B₁ and contact pads 116B₂. Some of connectors 120, such as connectors 120 ₁, are mounted on contact pads 116B₁, and some of connectors 120, such as connectors 120 ₂, are mounted on contact pads 116B₂. Connectors 120 may be ball grid array (BGA) balls. Connectors 120 may be used to electrically connect device package 100 to other package components such as another device die, an interposer, a package substrate, a printed circuit board, a mother board, and the like. Connectors 120 may have a thickness ranging from about 100 μm to about 300 μm. In some embodiments, each of connectors 120 ₁ and 120 ₂ has substantially the same size (including thickness and width). In some embodiments, uneven top surfaces of connectors 120 ₁ and 120 ₂ resulting from total thickness variance T are compensated or negated by the warpage of device package 100 when device package 100 is bonded with other package components.

A molded underfill 124 may be disposed over redistribution layer 116R and around connectors 120 to provide structural support to connectors 120 and/or protection to underlying device layers. In some embodiments, the molded underfill 124 includes a material the same as or similar to that of molding compound 104 for reducing warpage resulting from coefficient of thermal expansion (CTE) differences. In other embodiments, molded underfill 124 includes a material different from that of molding compound 104 for other applications. Molded underfill 124 may also be formed by a transfer molding process and therefore have a non-planar top surface. Alternatively, molded underfill 124 may be formed by any other suitable molding process.

FIGS. 2 through 9 illustrate cross-sectional views of intermediary stages of forming a device package 200 in accordance with some embodiments. Referring to FIG. 2, dies 102 are mounted on a carrier 142. Carrier 142 provides temporary mechanical and structural support to the dies 102 during subsequent processing steps. In this manner, damage to dies 102 is reduced or prevented. Carrier 142 may include, for example, glass, silicon oxide, aluminum oxide, and the like. A temporary adhesive layer 144 (e.g., a glue layer, a light-to-heat conversion (LTHC) coating, an ultraviolet (UV) film, and the like) is disposed over carrier 142. In addition, dies 102 may be temporarily affixed to carrier 142 using a die attach film (DAF)) (not shown) disposed on a backside of dies 102. In some embodiments, the die attach film is an epoxy resin, a phenol resin, acrylic rubber, silica filler or a combination thereof.

FIGS. 3 through 5 illustrate a transfer molding process. Referring to FIG. 3, a carrier 142 (having dies 102 mounted thereto) is positioned between a bottom plate 152 and a top plate 154 of a molding apparatus 150. Top and bottom plates 152 and 154 may include a suitable material for providing structural support such as a metal, ceramic, or the like.

In some embodiments, a polymer layer 156 is disposed on top plate 154 (e.g., facing dies 102). Polymer layer 156 may include a lamination film material, such as polyimide, PBO, epoxy, an underfill film, a molded underfill film, and the like either with or without a filler material. Polymer layer 156 may be compressible such that it may be shaped by dies 102 when polymer layer 156 contacts to dies 102. In some embodiments, polymer layer 156 has a thickness ranging from about 10 μm to about 100 μm. In some embodiments, a release film (not shown) is disposed between top plate 154 and polymer layer 156.

Afterwards, referring to FIG. 4, top and bottom plates 152 and 154 are pressed together, and polymer layer 156′ contacts the top surface of dies 102. Polymer layer 156′ may cover the top surface of dies 102 (e.g., cover pads 110 and passivation layer 112). Gaps 160 may remain disposed between dies 102 and under polymer layer 108. The lack of any support material under polymer layer 156′ may result in a non-planar bottom surface 156B′ of polymer layer 156′. For example, as shown in FIG. 4, polymer layer 156′ is partially compressed by dies 102. A portion of bottom surface 156B′ of polymer layer 156′ in the gaps 160 is lower than top surface 112A of passivation layer 112. In some embodiments, non-planar bottom surface 156B′ in the gaps 160 includes a non-planar portion recessed from top surface 112A of passivation layer 112. In some embodiments, bottom surface 156B′ further includes a substantially flat portion away from dies 102. Prior to its placement on dies 102, polymer layer 156′ may be uncured or only partially cured. Non-planar bottom surface 156B′ of polymer layer 156′ may have a total thickness variation T (e.g., distance between a highest point and a lowest point of the bottom surface) of about 1 μm to about 10 μm. Total thickness variation T may be a variable of the spacing of dies 102.

Afterwards, referring to FIG. 5, molding compound 104 is formed in gaps 160. In some embodiments, molding compound 104 is dispensed between dies 102 (e.g., in gaps 160) in liquid form. Molding compound 104 may not flow over top surfaces of dies 102 since it is sealed by polymer layer 156′. Afterwards, a curing process may be performed to solidify molding compound 104. During the molding process, top surface 104A of molding compound 104 may contact bottom surface 156B′ of polymer layer 156, and thus top surface 104A of molding compound 104 may have a similar profile as the bottom surface 156B′ of polymer layer 156′. As a result, top surface 104A of molding compound 104 is a non-planar surface recessed from the top surfaces of dies 102. For example, top surface 104 of molding compound 104 may be recessed from the top surface 112A of passivation layer 112. In some embodiments, top surface 104A of molding compound 104 includes a curved or linear inclined portion recessed from the top surface of dies 102. In some embodiments, top surface 104A of molding compound 104 further includes a substantially flat portion away from dies 102. Due to the similar profile as the bottom surface 156B′ of polymer layer 156, top surface 104A of molding compound 104 also has the total thickness variation T (e.g., distance between a highest point and a lowest point of the top surface) of about 1 μm to about 10 μm.

Afterwards, referring to FIG. 6, when molding apparatus 150 is removed, top surfaces of pads 110, passivation layer 112 and molding compound 104, remain exposed. Top surface 104A of molding compound 104 may be treated by plasma for providing a cleaner and rougher surface for adhesion improvement.

Referring to FIG. 7, redistribution layer 116R is formed over passivation layer 112 and molding compound 104. The formation of redistribution layer 116R may include depositing a seed layer (not shown), coating a photoresist layer (not shown) over the seed layer, forming various openings to define the shape of contact pads 116B₁ and 116B₂ and redistribution lines 116C by a lithography process, filling the openings in the mask layer using an electro-chemical plating process, and removing the seed layer from exposed areas, for example. An exemplary photolithography process may include processing steps of photoresist coating, soft baking, photo-mask aligning, exposing through the photo-mask, post-exposure baking, developing photoresist and hard baking. The photoresist may then be removed. In such embodiments, the interconnect structure 116 is formed of a single redistribution layer 116R and may be formed using one photo-mask.

Afterwards, referring to FIG. 8, connectors 120 are mounted to contact pads 116C₁ and 116C₂. In some embodiments, connectors 120 are made of conductive materials, such as solder, solder alloy, copper, copper alloy, gold, or gold alloy, etc. The connectors 120 may be mounted to contact pads 116B₁ and 116B₂ by a solder reflow process. In some embodiments, connectors 120 have a thickness of about 100 μm to about 300 μm.

Afterwards, referring to FIG. 9, a molded underfill 124 is formed around connectors 120 ₁ and 120 ₂. Molded underfill 124 may be also formed by the transfer molding process and therefore have a non-planar top surface. Alternatively, molded underfill 124 may be formed by any other suitable molding process.

After the molded underfill 124 is formed, device package 200 is diced to form separated chip packages, such as package 100 as shown in FIG. 1. In some embodiments, the dicing of device package 200 includes placing device package 200 on a dicing tape; removing carrier 142; and dicing molding compound 104 along scribing lines SC to separate dies 102.

FIG. 10 shows a device package 300 in accordance with some embodiments.

Device package 300 is similar with device package 100 but with under bump metallurgy (UBM) structures 170 disposed under connectors 120. For example, at an intermediate stage of manufacturing device package 200, such as after the formation of redistribution layer 116R in FIG. 7, a passivation layer 172 is formed over redistribution layer 116R while exposing contact pads 116B₁ and 116B₂. Afterwards, UBM structures 170 are formed over contact pads 116B₁ and 116B₂ for achieving greater adhesion and barrier function between connectors 120 and contact pads 120B₁ and 120B₂. In some embodiments, passivation layer 172 includes silicon oxide, un-doped silicate glass, silicon oxynitride, polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB) although other suitable passivation materials may also be used. Passivation layer 172 may have a thickness ranging from about 10 μm to about 100 μm. In some embodiments, each of UBM structures 170 includes multi-layers of conductive materials such as Ti, Cu, Ni, Au, Ag, an alloy thereof or a combination thereof. Device package 300 as shown in FIG. 10 is formed after the formation of connectors 120 and molded underfill 124 and the dicing.

FIG. 11 shows a device package 400 in accordance with some embodiments. Device package 400 is similar with device package 100 but with an additional passivation layer 180 interposed between interconnect structure 116 and passivation layer 112 and molding compound 104. For example, in an intermediate stage of manufacturing device package 200, such as after the formation of molding compound 104 as shown in FIG. 6, additional passivation layer 180 is formed over passivation layer 112 and molding compound 104 while exposing pads 110. Afterwards, interconnect structure 116 is formed over pads 110 and additional passivation layer 180. In some embodiments, device package 400 as shown in FIG. 11 is formed after the formation of connectors 120 and molded underfill 124 and the dicing. In other embodiments, device package 500 as shown in FIG. 12 is formed by similar steps with device package 400 except that UBM structures 170 and passivation layer 172 are formed before the formation of connectors 120.

FIG. 13 shows a device package 600 in accordance with some embodiments. Device package 600 may include a plurality of dies 102. For example, device package 600 may include two dies 102 disposed within molding compound 104 although any number of dies 102 may be included in device package 600. In some embodiments, at least two dies 102 are electrically connected to each other through redistribution line 116C on non-planar top surface 104A of molding compound 104. Device package 600 may be diced from device package 200 as shown in FIG. 9 with defining scribing lines in specific regions. In some embodiments, device package 600 also includes UBM structures 170 and/or passivation layer 180 over each die 120 and molding compound 104.

FIG. 14 shows a device package 700 in accordance with some embodiments. Device package 700 is similar with device package 100 but includes connectors 720 ₁ and 720 ₂ that have different volumes to each other. For example, connectors 720 ₂ may have a greater volume than that of connectors 720 ₁, which makes connectors 720 ₂ have a greater thickness and a greater width than that of connectors 720 ₁. Due to the thickness difference between connectors 720 ₁ and 720 ₂, top surfaces of connectors 720 ₁ and 720 ₂ may be level with each other to facilitate device package 700 to bond other package components in the presence of total thickness variance T and package warpage. In some embodiments, the thickness difference between connectors 720 ₁ and 720 ₂ is substantially the same as the total thickness variance T although the thickness difference can be any suitable value.

FIG. 15 shows a device package 800 in accordance with some embodiments in the present disclosure. Device package 800 is similar with device package 100, but contact pads 816B₁ have a surface area different from that of contact pads 816B₂. Connectors 820 ₂ on contact pads 816B₂ may have different thicknesses to each other while each of connectors 820 ₁ and 820 ₂ has substantially the same volume. For example, contact pads 816B₁ have a smaller surface area than that of contact pads 816B₂, and connectors 820 ₂ on contact pads 816B₂ have a greater thickness than that of connectors 820 ₁ on contact pads 816B₁ while each of connectors 820 ₁ and 820 ₂ has substantially the same volume. Due to the thickness difference between connectors 820 ₁ and 820 ₂, top surfaces of connectors 820 ₁ and 820 ₂ may be level with each other to facilitate device package 800 to bond other package components in the presence of total thickness variance T and package warpage. In some embodiments, the thickness difference between connectors 820 ₁ and 820 ₂ is substantially the same as the total thickness variance T although the thickness difference can be any suitable value.

FIG. 16 illustrates a method 900 for forming a package in accordance with various embodiments. The method 900 starts with operation 902, in which a plurality of dies is provided. Each of the plurality of dies includes pads surrounded by a passivation layer at a top surface of the dies. The method 900 continues to operation 904, in which a molding compound is formed around the plurality of dies. The molding compound has a non-planar top surface recessed from the top surface of dies. The method 900 continues to operation 906, in which interconnect structures are formed over the dies. At least one of the interconnect structures includes a redistribution layer extending onto the molding compound and being conformal to the non-planar top surface of the molding compound. The method 900 continues to operation 908, in which connectors are mounted to the interconnect structures. The method 900 continues to operation 910, in which the molding compound is diced to separate the plurality of dies.

The embodiments of the present disclosure offer advantages over existing art, though it is understood that other embodiments may offer different advantages, not all advantages are necessarily discussed herein, and that no particular advantage is required for all embodiments. By utilizing the disclosed device package and its manufacturing method, the overall thickness and fabrication cost can be reduced because the fan-out interconnect structure is directly disposed on the die and a non-planar surface of the molding compound. A planarization layer for planarizing the top surface of the molding compound is omitted.

In accordance with an embodiment, a device package includes a die and a molding compound around the die. The molding compound has a non-planar surface recessed from a top surface of the die. The device package also includes an interconnect structure disposed over the die. The interconnect structure includes a redistribution layer extending onto the molding compound and being conformal to the non-planar surface of the molding compound. The device package further includes a first connector disposed over the die and mounted onto the interconnect structure.

In accordance with another embodiment, a device package includes a first die and a second die disposed within a molding compound. The molding compound comprises a non-planar top surface recessed from the first die and the second die. The device package also includes a first interconnect structure disposed over the first die and extending onto the non-planar top surface of the molding compound. The first interconnect structure includes a first contact pad disposed over the first die. The device package further includes a second interconnect structure disposed over the first die and extending onto the non-planar top surface of the molding compound. In addition, the device package includes a redistribution line disposed over the non-planar surface of molding compound and extending form the first interconnect structure to the second interconnect structure. Furthermore, the device package includes a first connector mounted onto the first contact pad.

In accordance with yet another embodiment, a method for forming a device package includes providing a plurality of dies. The method also includes forming a molding compound around the plurality of dies. The molding compound has a non-planar top surface recessed from top surfaces of the dies. The method further includes forming interconnect structures over the plurality of dies. Each of the interconnect structures includes a redistribution layer extending onto the molding compound and being conformal to the non-planar surface of the molding compound. In addition, the method includes mounting connectors onto the interconnect structures. The method includes dicing the molding compound to separate the plurality of dies.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. 

What is claimed is:
 1. A device package comprising: a die; a molding compound around the die and having a non-planar top surface recessed from a top surface of the die; and an interconnect structure disposed over the die, wherein the interconnect structure comprises a redistribution layer extending onto the molding compound and being conformal to the non-planar surface of the molding compound.
 2. The device package of claim 1, further comprising a first connector mounted on a first contact pad and a second connector mounted on a second contact pad.
 3. The device package of claim 2, wherein the first connector and the second connector have a thickness difference.
 4. The device package of claim 3, wherein the first connector and the second connector have different volumes, and the thickness difference is attributed from the different volumes between the first connector and the second connector.
 5. The device package of claim 4, wherein the first contact pad and the second contact pad have different surface areas, wherein the thickness difference is attributed from the different surface areas between the first contact pad and the second contact pad.
 6. The device package of claim 2, wherein the interconnect structure further comprises under bump metallurgy (UBM) structures disposed over the first contact pad and the second contact pad.
 7. The device package of claim 2, further comprising a molded underfill around the first connector and the second connector.
 8. The device package of claim 1, wherein the non-planar surface of the molding compound comprises a curved or linear inclined portion adjacent to the die and a substantially flat portion on a side of the curved or linear inclined portion away from the die.
 9. The device package of claim 1, wherein the non-planar surface of the molding compound has a total thickness variance of about 1 μm to about 10 μm.
 10. The device package of claim 1, further comprising a second passivation layer disposed over the die and the molding compound and being conformal to the non-planar top surface of the molding compound, wherein the redistribution layer is formed over the second passivation layer.
 11. The device package of claim 1, wherein the interconnect structure is the redistribution layer.
 12. The device package of claim 1, wherein the molding compound has a top surface having a thickness variation of about 1 μm to about 10 μm.
 13. A device package comprising: a first die and a second die disposed within a molding compound, wherein the molding compound comprises a non-planar top surface recessed from the first die and the second die; a first interconnect structure disposed over the first die and extending onto the non-planar top surface of the molding compound, wherein the first interconnect structure comprises a first contact pad disposed over the first die; a second interconnect structure disposed over the first die and extending onto the non-planar top surface of the molding compound; a redistribution line disposed over the non-planar top surface of the molding compound and extending form the first interconnect structure to the second interconnect structure; and a first connector mounted onto the first contact pad.
 14. The device package of claim 13, wherein the redistribution line and the first contact pad are formed in the same layer.
 15. The device package of claim 13, wherein the at least one of the first interconnect structure and the second interconnect structure comprises a second contact pad disposed over the molding compound, wherein the package further comprises a second connector mounted onto the second contact pad.
 16. The device package of claim 13, wherein the first die and the second die are electrically connected through the redistribution line.
 17. A method for forming a device package comprising: providing a plurality of dies; forming a molding compound around the plurality of dies, wherein the molding compound has a non-planar top surface recessed from the top surfaces of the dies; forming an interconnect structure over the dies, wherein the interconnect structure comprises a redistribution layer in direct contact and conformal to the non-planar surface of the molding compound; mounting connectors onto the interconnection structures; and dicing the molding compound to separate the plurality of dies.
 18. The method of claim 17, wherein forming the molding compound comprises: pressing a compressible polymer to top surfaces of the plurality of dies; injecting a molding material around the plurality of dies; curing the molding material to form the molding compound; and removing the compressible polymer.
 19. The method of claim 17, further comprising: mounting connectors over the interconnect structure; and forming a molded underfill around the interconnect structure.
 20. The method of claim 17, wherein forming the interconnect structure further comprises forming UBM structures over the redistribution layer. 